The present invention concerns a MOS integrated semiconductor memory with memory locations arranged in lines and columns. Each memory location contains two one-transistor memory cells, whereby per memory location in each case two MOS transistors of the two one-transistor memory cells are selectable together by means of a word line which preferably runs in a line direction. The two MOS transistors in each case are coupled onto a bit line at each side of the memory location and which runs preferably in a column direction. Gates of the transistors and one electrode of the memory capacitors of the on-transistor memory location are each formed by a second polysilicon layer and a first polysilicon layer, respectively.
The essential construction of one transistor memory cells is known from "Siemens Research and Development Report", volume 4, (1975), No. 4, pages 197 to 202, incorporated herein by reference.
Further, MOS integrated semiconductor memories of the above mentioned kind are known from "1976 I.E.E.E. International Solid-State Circuits Conference", pages 128 and 129, incorporated herein by reference.
The principle construction of a single one-transistor memory cell of such a semiconductor memory may be seen in the perspective representation according to FIG. 1. There, in a semiconductor substrate 10, which consists, as a rule of silicon, an active area 12 for the one-transistor memory cell is defined by means of local thick oxide 11 (produced according to the so-called Locos method). Above this active area there are located a first conducting layer 15 of polycrystalline silicon, which represents an electrode of the memory capacitor of the one-transistor memory cell, as well as a second layer 16 out of polycrystalline silicon, which forms the gate electrode of the MOS transistor of the one-transistor memory cell. By means of insulating layers 13 and 14 (as a rule silicon dioxide layers), the layers 15 and 16 are separated both from the active layer 12 as well as from one another. The layers 15 and 16 lie in each case in a common plane. On each side of the one transistor memory cell, a bit line 17 or 18 is provided as shown. The bit line 18 is associated with the one-transistor memory cell shown, whereas the bit line 17 is associated to a further one-transistor memory cell, not shown here, which is provided at the memory location with the one-transistor memory cell shown. For selection of the one-transistor memory cells via the gates of the transistors, perpendicular to the bit lines 17 and 18 there is a metal word line 20 which is insulated by means of an insulation layer 19. Word line 20 contacts the gate electrode 16 of the MOS transistor of the one-transistor memory cell at location 21.
The layout of two one-transistor memory cells in one memory location of the semiconductor memory is visible in the top view of FIG. 2. Here, the same elements as in FIG. 1 are provided with the same reference symbols. From this illustration, one can see how the first conducting layer 15 represented with a dotted line is structured out of polycrystalline silicon, in order to form an electrode of two MOS memory capacitors from two one-transistor memory cells which are provided in one memory location. The second conducting layer 16 of polycrystalline silicon, which is represented with an unbroken line, is correspondingly structured in order to form a cohesive gate (transfer gate) for the two MOS transistors of the one-transistor memory cell which is encompassed in one memory location.
The two bit lines 17 and 18 are diffused zones and run in each case on one side of the memory cells. The diffusions in the area of the transfer gate which is formed by the second conducting layer 16 out of polycrystalline silicon extend up to this second conducting layer.
The word line 20 which is not represented in FIG. 2 runs vertically over the bit lines 17 and 18, whereby the contacting proceeds with the transfer gate which is formed by the second conducting layer 16 out of polycrystalline silicon at the contact location 21. Areas 22 and 22' which are represented in hatched form, show the active areas of the MOS memory capacitors of the one-transistor memory cells. In the case of a semiconductor memory of the above type, a relatively large area requirement results because of the direction of the bit lines as diffused zones on, in each case, one side of the memory cells. Above and beyond this, the memory capacitance is limited because of the dimensions of the first conducting layer 15 of polycrystalline silicon which is limited by the bit lines. Also a capacitance of the bit line is relatively large.